LDMOS devices are the devices of choice in the 20-60V range. LDMOS devices are very easy to integrate into a CMOS or BiCMOS process thereby facilitating the fabrication of control, logic, and power switches on a single chip. In the 20-60V range, optimized LDMOS devices are also much more efficient in terms of on-state voltage and switching losses than power bipolar junction transistors or other hybrid MOSbipolar devices.
Optimized LDMOS design seeks to provide power switches with very low specific on-state resistance (Rsp) while maintaining high switching speed. A low Rsp helps reduce power losses as well as the size of the die. RESURF LDMOS or RLDMOS devices are very attractive in this respect as they offer very good trade-off between Rsp and breakdown voltage (BV) capability compared to non-RLDMOS devices. RLDMOS devices use the Reduced Surface electric field phenomenon to increase the drift region doping for a given breakdown voltage. The increased drift region doping causes reduction in the drift region resistance leading to an overall lower Rsp for the device.
As device size shrinks, the desire to maintain as wide a Safe Operating Area (SOA) as possible remains, since the applications these devices are used in remain the same. However, shrinking RESURF LDMOS device size has a negative impact on the robustness of the device. Accordingly, a need exists for a RESURF LDMOS device having improved robustness.